(1) Field of the Invention
The invention relates to a new design for an electrically erasable and programmable read only memory device of the flash type, formed within a semiconductor body, and the method for building the device.
(2) Description of the Prior Art
Conventional Field Effect Transistor (FET) devices consist of a source, a drain, and a control gate. These devices, when used in memory structures, are classified as volatile since they remain `on` or `off` only for as long as external voltage is applied to the control gate. In Electrically Erasable and Programmable Read Only Memories (EEPROMs), what was formerly the control gate is replaced by an (electrically) floating gate and a fourth element (the `new` control gate) is added to the device.
When voltage is applied to the control gate of an EEPROM, charge is passed to the floating gate so that it functions in the same manner as the control gate of a conventional FET. The geometry of an EEPROM is such that, once voltage is removed from the control gate, the charge on the floating gate remains intact, a relatively large voltage in the reverse direction being required to remove said charge and thus return the floating gate to its original state.
The asymmetry in the voltages needed to charge and discharge the floating gate is accomplished by providing the floating gate with sharp points or edges and then locating the control gate in close proximity to the sharp points or edges. Because of high field emission from regions having a small radius of curvature, electrons are able to flow from the floating gate into the control gate at relatively low voltages whereas electron flow in the reverse direction is much more difficult and requires the application of substantially higher voltage.
Previous designs of EEPROMs have relied on the intersection of a diffusion region with the surface to provide the aforementioned sharp edge (see, for example, U.S. Pat. No. 4,975,383 by David A. Baglee, Dec. 4, 1990). In the present invention a novel method for creating a much sharper edge is disclosed.
Because of the need to provide good coupling between the control and floating gates, in most EEPROMs (particularly the flash type) these gates are relatively large, making for a fairly bulky overall device. In the present invention this problem is significantly reduced by designing the floating gate so that much-of it lies below the surface. A similar approach was followed by Baglee (above) but in the present invention the method for achieving this is quite different.